1. Field of the Invention
The present invention relates to a programming/erasing method, and more particularly, to a programming/erasing method that effectively improves slow program/erase bit induced by process variation.
2. Description of the Prior Art
In nonvolatile memory applications, the data is processed by programming and erasing the memory cells of the memory array. Each action of programming or erasing is followed by a verification step. The verification step is to verify if the memory cell being programmed or erased are compliant to the specification. The verification step includes verifying criterions such as the current, voltage, or threshold voltage etc., of the programmed memory cell.
Due to process variation, the issue of slow program/erase bit arises. Slow program/erase bit occurs when a memory cell does not meet the desired criterion after being programmed or erased. Slow program/erase bit does not necessarily mean the particular memory cell is a failure. However the particular memory cell may take several programming or erasing retries for it to meet the verification criterion. Alternatively, the particular memory cell may still fail after several programming attempts. As a result, slow program/erase bit not only delays the program or erase time, but also causes the low production yield.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating the conventional constant pulses for programming a nonvolatile memory. The conventional constant pulse program method programs a memory cell with a voltage VCONSTANT. If the programmed memory cell fails the programming verification, the constant pulse program method re-programs the memory cell with the same voltage VCONSTANT again. For instance, as shown in FIG. 1, with six pulses of the constant voltage VCONSTANT indicates the constant pulse program method has programmed the memory cell for six times.
Please refer to FIG. 2. FIG. 2 is a flowchart illustrating the conventional constant pulse program method. The conventional constant pulse program method programs the nonvolatile memory with constant voltage pulses. The conventional constant pulse program method includes the following steps:
Step 200: Start and set a counter N to 0.
Step 201: Apply the voltage VCONSTANT to the memory cell.
Step 202: Perform a programming verification PV to verify the programmed memory cell is compliant to the criterion; if the verification passes, go to Step 205; otherwise, go to Step 203.
Step 203: Perform a program constrain check to verify if the program constrains have been exceeded; for example, if the number of times the memory cell has been programmed has exceeded a predetermined value n, or if the total programming time T has exceeded a predetermined time t; if exceeded, go to Step 205; otherwise, go to Step 204.
Step 204: The counter N is increased by 1 to indicate the number of times the memory cell has been programmed, and then go to Step 201.
Step 205: End.
The constant pulse program method requires a relatively simple peripheral circuit design. The constant pulse program method raises low component disturbance. However the constant pulse program method is inclined to the occurrence of slow program/erase bit.
Please refer to FIG. 3. FIG. 3 is a diagram illustrating the conventional ramping pulses for programming a nonvolatile memory. The ramping pulse program method requires a sensing circuit to provide a feedback if the programming verification is failed. The programming voltage of the ramping pulse program method is varied according to the feedback of the sensing circuit. For instance, the ramping pulse program method programs a memory cell with the voltage VRAMP—0. If the programmed memory cell fails the programming verification, the sensing circuit provides a feedback according to the failed specification. The ramping pulse program method then programs the memory cell with the voltage VRAMP—1 according to the feedback of the sensing circuit. If the programmed memory cell fails the programming verification again, the sensing circuit provides another feedback accordingly. The ramping pulse program method programs the memory cell with the voltage VRAMP—2 according to the feedback of the sensing circuit and so on. The number of ramping levels is theoretically indefinite and normally a ramping range is required for limiting the ramping voltage. Generally the voltage VRAMP—1 is greater than the voltage VRAMP—0. In other words, the VRAMP—N is greater than the VRAMP—N-1. However, there are few occasions when the VRAMP−N-1 is greater than the voltage VRAMP−N.
Please refer to FIG. 4. FIG. 4 is a flowchart illustrating the conventional ramping pulse program method. The ramping pulse program method programs the nonvolatile memory with pulses of varying voltages. The conventional ramping pulse program method includes the following steps:
Step 400: Start and set a counter N to 0.
Step 401: Apply the voltage VN to the memory cell.
Step 402: Perform a programming verification PV to verify the programmed memory cell is compliant to the criterion; if the verification passes, go to Step 405; otherwise, go to Step 403.
Step 403: Perform a program constrain check to verify if the program constrains have been exceeded; for example, if the number of times the memory cell has been programmed has exceeded a predetermined value n, or if the total programming time T has exceeded a predetermined time t; if exceeded, go to Step 405; otherwise, go to Step 404.
Step 404: The counter N is increased by 1 to indicate the number of times the memory cell has been programmed.
Step 405: End.
Every time the memory cell is re-programmed, the counter N is incremented and resulting in varying the voltage VN of the next instance of re-programming. Each time the voltage VN is varied indicates the memory cell is being programmed with a voltage with a different voltage level. The ramping pulse program method requires a relatively complex peripheral circuit design due to the demand of a sensing circuit. The variation of the voltage VN is according to the feedback of the sensing circuit. Also, because of the ramping characteristics, the voltage applied to programmed memory cell is higher than the surrounding memory cells in the memory array. Therefore, the ramping pulse program method not only stresses the programmed memory cell but also cause disturbance to other memory cells.
Therefore, both the constant pulse program method and the ramping pulse program method are unable to solve the slow program/erase bit issue while maintaining a simple peripheral circuit design and low component disturbance.